In recent years, a bit rate required in an optical transmission system has been increasing. Moreover, as a result of the progress in the speed and the integration of an electronic device technology, a digital coherent scheme of carrying out synchronous detection of an optical signal can be achieved, and multi-level modulation/demodulation technologies such as quadrature phase-shift keying (QPSK) and 16-quadrature amplitude modulation (16QAM) are employed.
As compared to intensity modulated direct detection (IM-DD) and differential phase-shift keying (DPSK), which have hitherto been employed, the multi-level modulation/demodulation technologies such as the QPSK and the 16QAM have a short interval between signal points, and a higher signal noise ratio (SNR) is thus required in order to achieve an equivalent transmission distance and signal speed.
In order to compensate this insufficiency in the SNR, an error correction decoding scheme acquired by combining a strong error correction code, e.g., a low density parity check (LDPC) code, with soft decision decoding that also uses analog information on the signal is usually used. The soft decision decoding calculates likelihoods of bits assigned to a signal point of a received signal based on a position of the signal point, and carries out error correction.
Meanwhile, in the field of the wireless communication, the application of the multi-level modulation/demodulation technology has been in progress, and many communication standards such as the worldwide interoperability for microwave access (WiMAX) and the long term evolution (LTE) are established. In order to use the same apparatus and device to meet those standards, such a configuration that a likelihood calculation circuit is shared among a plurality of communication standards is conceivable.
For example, in Patent Literature 1, there is disclosed a method of applying, in the WiMAX and LTE, a simple rotation or inversion to a received signal to process a bit mapped to different signal points in the same likelihood generation circuit, to thereby decrease a required hardware amount.